1. Technical Field
The present disclosure relates to analog to digital converters, and more particularly to an analog to digital converter provided with a pulse delay circuit including a plurality of delay units connected with each other, in order to perform an analog to digital conversion.
2. Description of the Related Art
A type of analog to digital converter utilizes the pulse delay circuit for the analog to digital conversion in which each delay unit delays a pulse signal with a delay time corresponding to an input voltage.
Conventionally, this type of analog to digital converter is known as a Time Analog to Digital converter, i.e., TAD, that is constituted by digital circuit, and the TAD enables fast analog to digital conversion.
As an example of the TAD, Japanese Patent Application Laid-Open Publication No. 1993-259907 discloses a TAD having the following configuration. FIG. 1 is a block diagram showing a configuration of the TAD disclosed in the above-described patent document.
As shown in FIG. 1, the TAD 10 is provided with a ring delay line 11 (hereinafter is called as RDL 11) in which a plurality of delay units are electrically connected with each other in the form of a ring shape. The TAD 10 is configured to delay a pulse signal by a delay time corresponding to an analog input voltage Vin. The delay unit included in the RDL 11 is constituted by a NAND circuit (as first stage of the RDL 11) and a plurality of inverter circuit INVs (the number of inverter circuits is even number). The NAND circuit receives a pulse signal PA at an input terminal of the RDL 11 and the plurality of inverter circuits INVs is configured to invert the pulse signal and output the inverted pulse signal.
The TAD 10 includes a counter 12, a latch circuit 13, a pulse selector 14, an encoder 15 and a signal processing circuit 16. The counter 12 counts the number of times the pulse signal circulates in the RDL 11 by counting the number of inversions of the output level at the last-stage delay unit in the RDL 11 and generates a numerical data. The latch circuit 13 latches the numerical data generated by the counter 12 at a measurement timing indicated by a pulse signal PB. The pulse selector 14 is configured to acquire the output of the delay unit that constitutes the RDL 11 at the measurement timing of the pulse signal PB, determine the output level so as to extract a pulse signal that circulates in the RDL 11 and generate a signal indicating the location where the pulse signal is circulating in the RDL 11. The encoder 15 generates numerical data corresponding to the output signal from the pulse selector 14. The signal processing circuit 16 is configured to receive the numerical data from the latch circuit 13 and the encoder 15 such that the numerical data outputted by the latch circuit 13 as upper bits and the numerical data outputted by the encoder 15 as lower bits are inputted to the signal processing circuit 16, and add the upper bits and the lower bits whereby the signal processing circuit 16 generates numerical data DT indicating the number of delay units (NAND, INV) where the pulse signal passes through within a predetermined period defined by the period of pulse signal PB.
The pulse signal PA and PB is supplied by external control circuit and the TAD 10 converts the analog input voltage Vin during a period from the pulse signal PA is inputted to the TAD to the pulse signal PB is inputted to the TAD, and outputs AD conversion data DT which corresponds to average value of the input voltage Vin averaged during the above-described period.
Since the delay time at the delay unit (NAND circuit and INV circuit) has a temperature dependency, the delay time does not vary only depending on the input voltage Vin but also varies depending on the temperature. Generally, the higher the temperature, the larger the delay time. Hence, input-output characteristics of the TAD 10 (i.e., conversion characteristics between input voltage Vin and AD conversion data DT) have temperature dependency as well.
FIG. 2 is a graph showing an example of a measurement result for the input-output characteristics at the temperatures −40 degree C., 0 degree C. and 100 degree C. As shown in FIG. 2, in the input-output characteristics, a point where the input-output characteristics are constant regardless of the temperature, exists. Hereinafter the point where the input voltage Vin has no temperature dependency is called no temperature dependency voltage Vf (i.e., temperature independent voltage Vf).
A fluctuation in the AD conversion data DT due to temperature variation is extremely low around the temperature independent voltage Vf and the fluctuation becomes larger when the input voltage Vin moves apart from the temperature independent voltage Vf. That is to say, when the input voltage Vin fluctuates around the temperature independent voltage Vf, influence of the temperature variation can be suppressed.
The temperature independent voltage Vf can be designed to be within a given voltage range by controlling a process parameter in the manufacturing process, e.g. CMOS process, such as threshold voltage of MOS transistors in the delay unit. However, at the moment, the temperature independent voltage is difficult to control to the desired voltage value by using the adjustable process parameters.